/*
 * sor_regs_t19x.h: T19x SOR register definitions
 *
 * Copyright (c) 2017-2018, NVIDIA CORPORATION, All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 */

#ifndef __DRIVER_VIDEO_TEGRA_DC_SOR_REGS_T19X_H__
#define __DRIVER_VIDEO_TEGRA_DC_SOR_REGS_T19X_H__

/*
 * Group A
 *
 * Existing registers with new offsets:
 * (1) SOR_NV_PDISP_HEAD_STATE1_0 ... SOR_NV_PDISP_HEAD_STATE5_0
 * (2) SOR_NV_PDISP_SOR_PLL0_0 ... SOR_NV_PDISP_SOR_PLL4_0
 * (3) SOR_NV_PDISP_SOR_DP_PADCTL0_0 ... SOR_NV_PDISP_SOR_DP_PADCTL3_0
 * (4) SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0
 * (5) SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0
 * (6) SOR_NV_PDISP_DP_INT_ENABLE_0
 */
#define NV_HEAD_STATE0_T19X(i)	(0x151 + i)
#define NV_HEAD_STATE1_T19X(i)	(0x155 + i)
#define NV_HEAD_STATE2_T19X(i)	(0x159 + i)
#define NV_HEAD_STATE3_T19X(i)	(0x15d + i)
#define NV_HEAD_STATE4_T19X(i)	(0x161 + i)
#define NV_HEAD_STATE5_T19X(i)	(0x165 + i)

#define NV_SOR_PLL0_T19X	(0x169)
#define NV_SOR_PLL1_T19X	(0x16a)
#define NV_SOR_PLL2_T19X	(0x16b)
#define NV_SOR_PLL3_T19X	(0x16c)
#define NV_SOR_PLL4_T19X	(0x16d)

#define NV_SOR_DP_PADCTL_T19X(i)	(0x16e + i)

#define NV_SOR_DP_MISC1_OVERRIDE_T19X	(0x173)
#define NV_SOR_DP_MISC1_BIT6_T19X	(0x174)

#define NV_SOR_DP_INT_ENABLE_T19X	(0x177)
/* Group A */


/*
 * Group B
 *
 * Existing registers with new fields:
 * (1) SOR_NV_PDISP_SOR_STATE1_0
 *     - ASY_CHROMA_V_DECIMATE [25:25]
 * (2) SOR_NV_PDISP_SOR_DP_LINKCTL0_0
 *     - ASYNC_FIFO_BLOCK [01:01]
 * (3) SOR_NV_PDISP_SOR_PLL4_0
 *     - SLOWCLK_OUT [16:13]
 *     - MACROPLL_LOCK_READY [00:00]
 */
#define NV_SOR_STATE1_ASY_CHROMA_V_DECIMATE_SHIFT	(25)
#define NV_SOR_STATE1_ASY_CHROMA_V_DECIMATE_MASK	(0x1 << 25)
#define NV_SOR_STATE1_ASY_CHROMA_V_DECIMATE_DISABLE	(0 << 25)
#define NV_SOR_STATE1_ASY_CHROMA_V_DECIMATE_ENABLE	(1 << 25)

#define NV_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_SHIFT	(1)
#define NV_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_MASK		(0x1 << 1)
#define NV_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_NO		(0 << 1)
#define NV_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_YES		(1 << 1)

#define NV_SOR_PLL4_MACROPLL_LOCK_READY_SHIFT	(0)
#define NV_SOR_PLL4_MACROPLL_LOCK_READY_MASK	(0x1 << 0)
#define NV_SOR_PLL4_MACROPLL_LOCK_READY_NO	(0 << 0)
#define NV_SOR_PLL4_MACROPLL_LOCK_READY_YES	(1 << 0)
/* Group B */


/*
 * Group C
 *
 * Existing registers with additional field enum values:
 * (1) SOR_NV_PDISP_SOR_STATE1_0
 *     - ASY_PIXELDEPTH [20:17]
 *       - BPP_12_420 (10)
 *       - BPP_15_420 (11)
 *       - BPP_18_420 (12)
 *       - BPP_24_420 (13)
 *     - ASY_OWNER [03:00]
 *       - HEAD3 (4)
 * (2) SOR_NV_PDISP_SOR_TEST_0
 *     - TESTMUX [31:24]
 *        - PLL_LOCK (1)
 *        - INTR_LOCK (3)
 *     - HEAD_NUMBER [15:12]
 *       - HEAD3 (4)
 * (3) SOR_NV_PDISP_SOR_DP_TPG_0
 *     - LANE3_PATTERN [27:24]
 *       - CP2520_PAT1 (9)
 *       - CP2520_PAT3 (10)
 *       - TRAINING4 (11)
 *     - LANE2_PATTERN ... LANE0_PATTERN
 *       - ...
 */
#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_12_420	(10 << 17)
#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_15_420	(11 << 17)
#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_420	(12 << 17)
#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_420	(13 << 17)
#define NV_SOR_STATE1_ASY_OWNER_HEAD3	(4 << 0)

#define NV_SOR_TEST_TESTMUX_PLL_LOCK		(1 << 24)
#define NV_SOR_TEST_TESTMUX_INTR_LOCK	(3 << 24)
#define NV_SOR_TEST_HEAD_NUMBER_HEAD3		(4 << 12)
/* Group C */


/*
 * Group D
 *
 * New registers:
 * (1) SOR_NV_PDISP_SOR_PLL5_0
 * (2) SOR_NV_PDISP_SOR_AFIFO_CTRL_0
 * (3) SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0
 */

/* NV_SOR_PLL5 START */
#define NV_SOR_PLL5_T19X			(0x179)

#define NV_SOR_PLL5_CLK_EN_DIFF_DET_SHIFT	(14)
#define NV_SOR_PLL5_CLK_EN_DIFF_DET_MASK	(0x1 << 14)
#define NV_SOR_PLL5_CLK_EN_DIFF_DET_DISABLE	(0 << 14)
#define NV_SOR_PLL5_CLK_EN_DIFF_DET_ENABLE	(1 << 14)

#define NV_SOR_PLL5_PLL_SEL_TIMER_SHIFT		(11)
#define NV_SOR_PLL5_PLL_SEL_TIMER_MASK		(0x7 << 11)
#define NV_SOR_PLL5_PLL_SEL_TIMER_TREF_2_15	(0 << 11)
#define NV_SOR_PLL5_PLL_SEL_TIMER_TREF_2_14	(1 << 11)
#define NV_SOR_PLL5_PLL_SEL_TIMER_TREF_2_13	(2 << 11)
#define NV_SOR_PLL5_PLL_SEL_TIMER_TREF_2_12	(3 << 11)
#define NV_SOR_PLL5_PLL_SEL_TIMER_TREF_2_11	(4 << 11)
#define NV_SOR_PLL5_PLL_SEL_TIMER_TREF_2_10	(5 << 11)
#define NV_SOR_PLL5_PLL_SEL_TIMER_TREF_2_9	(6 << 11)
#define NV_SOR_PLL5_PLL_SEL_TIMER_TREF_2_8	(7 << 11)

#define NV_SOR_PLL5_PLL_PD_TIMER_SHIFT		(10)
#define NV_SOR_PLL5_PLL_PD_TIMER_MASK		(0x1 << 10)
#define NV_SOR_PLL5_PLL_PD_TIMER_ENABLE		(0 << 10)
#define NV_SOR_PLL5_PLL_PD_TIMER_DISABLE	(1 << 10)

#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_FLOCK_SHIFT	(5)
#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_FLOCK_MASK	(0x1 << 5)
#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_FLOCK_ENABLE	(0 << 5)
#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_FLOCK_DISABLE	(1 << 5)

#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_RATIO_SHIFT		(1)
#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_RATIO_MASK		(0x3 << 1)
#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_RATIO_PLL_SEL_TIMER_1_2	(0 << 1)
#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_RATIO_PLL_SEL_TIMER_1_4	(1 << 1)
#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_RATIO_PLL_SEL_TIMER_1_8	(2 << 1)
#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_RATIO_PLL_SEL_TIMER_1_16	(3 << 1)

#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_EN_SHIFT		(0)
#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_EN_MASK		(0x1 << 0)
#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_EN_ENABLE	(0 << 0)
#define NV_SOR_PLL5_SETUP_LCKDET_TIMER_EN_DISABLE	(1 << 0)
/* NV_SOR_PLL5 END */

/* NV_SOR_AFIFO_CTRL START */
#define NV_SOR_AFIFO_CTRL	(0x17c)

#define NV_SOR_AFIFO_CTRL_AFIFOWATER_OVR_VAL_SHIFT	(1)
#define NV_SOR_AFIFO_CTRL_AFIFOWATER_OVR_VAL_MASK	(0x7 << 1)
#define NV_SOR_AFIFO_CTRL_AFIFOWATER_OVR_VAL_WATER(i)	(i << 1)

#define NV_SOR_AFIFO_CTRL_AFIFOWATER_OVR_SHIFT		(0)
#define NV_SOR_AFIFO_CTRL_AFIFOWATER_OVR_MASK		(0x1 << 0)
#define NV_SOR_AFIFO_CTRL_AFIFOWATER_OVR_DISABLE	(0 << 0)
#define NV_SOR_AFIFO_CTRL_AFIFOWATER_OVR_ENABLE		(1 << 0)
/* NV_SOR_AFIFO_CTRL END */

/* NV_SOR_FPGA_CLK_SEL START */
#define NV_SOR_FPGA_CLK_SEL	(0x17d)

#define NV_SOR_FPGA_CLK_SEL_FPGA_HDMI420_SEL_SHIFT	(1)
#define NV_SOR_FPGA_CLK_SEL_FPGA_HDMI420_SEL_MASK	(0x1 << 1)
#define NV_SOR_FPGA_CLK_SEL_FPGA_HDMI420_SEL_DISABLE	(0 << 1)
#define NV_SOR_FPGA_CLK_SEL_FPGA_HDMI420_SEL_ENABLE	(1 << 1)

#define NV_SOR_FPGA_CLK_SEL_FPGA_PCLK_MUX_SEL_SHIFT	(0)
#define NV_SOR_FPGA_CLK_SEL_FPGA_PCLK_MUX_SEL_MASK	(0x1 << 0)
#define NV_SOR_FPGA_CLK_SEL_FPGA_PCLK_MUX_SEL_HDMI	(0 << 0)
#define NV_SOR_FPGA_CLK_SEL_FPGA_PCLK_MUX_SEL_DP	(1 << 0)
/* NV_SOR_FPGA_CLK_SEL END */

/* Group D */

#endif /* __DRIVER_VIDEO_TEGRA_DC_SOR_REGS_T19X_H__ */
